x86/amd: Try to set lfence as being Dispatch Serialising
authorAndrew Cooper <andrew.cooper3@citrix.com>
Sun, 17 Dec 2017 16:20:50 +0000 (16:20 +0000)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Tue, 16 Jan 2018 17:45:50 +0000 (17:45 +0000)
commitfe3ee5530a8d0d0b6a478167125d00c40f294a86
treecf464cd1c9cbf17a7312e4c42cb4b4875da70f34
parent31d6c53adf6417bf449ca50e8416e41b64d46803
x86/amd: Try to set lfence as being Dispatch Serialising

This property is required for the AMD's recommended mitigation for Branch
Target Injection, but Xen needs to cope with being unable to detect or modify
the MSR.

This is part of XSA-254.

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
xen/arch/x86/cpu/amd.c
xen/include/asm-x86/cpufeature.h
xen/include/asm-x86/cpufeatures.h
xen/include/asm-x86/msr-index.h